doc.# dsfp-hv20320 c071613 hv20320 low charge injection 8-channel high voltage analog switch block diagram sw0 sw1 sw2 sw3 sw4 sw5 sw6 sw7 latches level shifters output switches vdd le cl din clk dout 8-bit shift register d le cl d le cl d le cl d le cl d le cl d le cl d le cl d le cl vnn vpp features ? hvcmos ? technology for high performance ? very low quiescent power dissipation (-10a) ? output on-resistance typically 22 ? low parasitic capacitances ? dc to 50mhz small signal frequency response ? -60db typical output off isolation at 5.0mhz ? cmos logic circuitry for low power ? excellent noise immunity ? on-chip shift register, latch and clear logic circuitry ? flexible high voltage supplies applications ? medical ultraso und imaging ? piezoelectric transducer drivers general description this device is a low charge injection, 8-channel, high-voltage analog switch integrated circuit (ic) intended for use in appli - cations requiring high voltage switching controlled by low volt - age control signals, such as ultrasound imaging and printers. input data is shifted into an 8-bit shift register which can then be retained in an 8-bit latch. to reduce any possible clock feed-through noise, latch enable bar (le) should be left high until all bits are clocked in. using hvcmos ? technology, this switch combines high voltage bilateral dmos switches and low power cmos logic to provide effcient control of high volt - age analog signals. these ics are suitable for various combinations of high volt - age supplies, e.g., v pp /v nn : +50v/-150v, or +100v/-100v. supertex inc. supertex inc. www .supertex.com
2 doc.# dsfp-hv20320 c071613 hv20320 absolute maximum ratings parameter value v dd logic power supply voltage -0.5v to +15v v pp - v nn supply voltage 220v v pp positive high voltage supply -0.5v to v nn +200v v nn negative high voltage supply +0.5v to -200v logic input voltages -0.5v to v dd +0.3v analog signal range v nn to v pp peak analog signal current/channel 3.0a storage temperature -65 o c to +150 o c power dissipation 1.2w operating conditions sym parameter value v dd logic power supply voltage 1,3 4.5v to 13.2v v pp positive high voltage supply 1,3 40v to v nn +200v v nn negative high voltage supply 1,3 -40v to -160v v ih high level input voltage v dd -1.5v to v dd v il low-level input voltage 0v to 1.5v v sig analog signal voltage peak-to-peak v nn +10v tov pp -10v 2 t a operating free air temperature 0 o c to 70 o c absolute maximum ratings are those values beyond which damage to the device may occur. functional operation under these conditions is not implied. continuous operation of the device at the absolute rating level may affect device reliability. all voltages are referenced to device ground. notes: 1. power up/down sequence is arbtrary except gnd must be powered -up frst and powered down last. 2. v sig must be v nn v sig v pp or foating during power up/down transition. 3. rise and fall times of power supplies v dd , v pp , and v nn should not be less than 1.0msec. product marking 28-lead plcc 1 28 4 26 pin confguration 28-lead plcc (top view) yy = year sealed ww = week sealed l = lot number a = assembler id c = country of origin* = ?green? packaging *may be part of top marking top marking bottom marking yyww aaa hv20320pj llllllllll ccccccccccc package may or may not include the following marks: si or ordering information part number package option packing HV20230PJ-G 28-lead plcc 38/tube HV20230PJ-G m904 28-lead plcc 500/reel typical thermal resistance package ja 28-lead plcc 48 o c/w -g denotes a lead (pb)-free / rohs compliant package supertex inc. www .supertex.com
3 doc.# dsfp-hv20320 c071613 hv20320 dc electrical characteristics (over operating conditions unless otherwise specifed ) r ons small signal switch on-resis - tance - 30 - 26 38 - 48 i sig = 5.0ma v pp = +40v v nn = -160v - 25 - 22 27 - 32 i sig = 200ma - 25 - 22 27 - 30 i sig = 5.0ma v pp = +100v v nn = -100v - 18 - 18 24 - 27 i sig = 200ma - 23 - 20 25 - 30 i sig = 5.0ma v pp = +160v v nn = -40v - 22 - 16 25 - 27 i sig = 200ma r ons small signal switch on-resistance matching - 20 - 5.0 20 - 20 % i sig = 5.0ma, v pp = +100v, v nn = -100v r onl large signal switch on-resis - tance - - - 15 - - - v sig = v pp -10v, i sig = 1.0a i sol switch off leakage per switch - 5.0 - 1.0 10 - 15 a v sig = v pp -10v, v nn +10v v os dc offset switch off - 300 - 100 300 - 300 mv r l = 100k dc offset switch on - 500 - 100 500 - 500 mv r l = 100k i ppq quiescent v pp supply current - - - 10 50 - - a all switches off i nnq quiescent v nn supply current - - - -10 -50 - - a all switches off i ppq quiescent v pp supply current - - - 10 50 - - a all switches on, i sw = 5.0ma i nnq quiescent v nn supply current - - - -10 -50 - - a all switches on, i sw = 5.0ma i sw switch output peak current - 3.0 - 3.0 2.0 - 2.0 a v sig duty cycly < 0.1% f sw output switching frequency - - - - 50 - - khz duty cycle = 50% i pp supply current - 6.5 - - 7.0 - 8.0 ma v pp = +40v v nn = -160v all output switches are turning on and off at 50khz with no load - 4.0 - - 5.0 - 5.5 v pp = +100v v nn = -100v - 4.0 - - 5.0 - 5.5 v pp = +160v v nn = -40v i nn supply curent - 6.5 - - 7.0 - 8.0 ma v pp = +40v v nn = -160v all output switches are turning on and off at 50khz with no load - 4.0 - - 5.0 - 5.5 v pp = +100v v nn = -100v - 4.0 - - 5.0 - 5.5 v pp = +160v v nn = -40v i dd logic supply average current - 4.0 - - 4.0 - 4.0 ma f clk = 5.0mhz, v dd = 5.0v i ddq logic supply quiescent cur - rent - 10 - - 10 - 10 a --- i sor data out source current 0.45 - 0.45 0.70 - 0.40 - ma v out = v dd -0.7v i sink data out sink current 0.45 - 0.45 0.70 - 0.40 - ma v out = 0.7v c in logic input capacitance - 10 - - 10 - 10 pf --- sym parameter 0 o c +25 o c +70 o c unit conditions min max min typ max min max supertex inc. www .supertex.com
4 doc.# dsfp-hv20320 c071613 hv20320 sym parameter 0 o c +25 o c +70 o c unit conditions min max min typ max min max ac electrical characteristics (over recommended operating conditions: v dd = 5.0v, unless otherwise specifed) t sd set up time before le rises 150 - 150 - - 150 - ns --- t wle time width of le 150 - 150 - - 150 - ns --- t do clock delay time to data out - 150 - - 150 - 150 ns --- t wcl time width of cl 150 - 150 - - 150 - ns --- t su set up time data to clock 15 - 15 8.0 - 20 - ns --- t h hold time data from clock 35 - 35 - - 35 - ns --- f clk clock frequency - 5.0 - - 5.0 - 5.0 mhz 50% duty cycle, f data = f clk /2 t r , t f clock rise and fall times - 50 - - 50 - 50 ns --- t on turn on time - 5.0 - - 5.0 - 5.0 s v sig = v pp -10v, r load = 10k t off turn off time - 5.0 - - 5.0 - 5.0 s v sig = v pp -10v, r load = 10k dv/dt maximun v sig slew rate - 20 - - 20 - 20 v/ns v pp = +160v, v nn = -40v - 20 - - 20 - 20 v pp = +100v, v nn = -100v - 20 - - 20 - 20 v pp = +40v, v nn = -160v k o off isolation -30 - -30 -33 - -30 - db f = 5.0mhz, 1.0k/15pf load -58 - -58 - - -58 - f = 5.0mhz, 50 load k cr switch crosstalk -60 - -60 -70 - -60 - db f = 5.0mhz, 50 load i id output switch isolation diode current - 300 - - 300 - 300 ma 300ns pulse width, 2.0% duty cycle c sg(off) off capacitance sw to gnd 5.0 17 5.0 12 17 5.0 17 pf 0v, f = 1.0mhz c sg(on) on capacitance sw to gnd 25 50 25 38 50 25 50 pf 0v, f = 1.0mhz +v spk output voltage spike - - - - 150 - - mv v pp = +40v, v nn = -160v, r load = 50 -v spk - - - - 150 - - +v spk - - - - 150 - - v pp = +100v, v nn = -100v, r load = 50 -v spk - - - - 150 - - +v spk - - - - 150 - - v pp = +160v, v nn = -40v, r load = 50 -v spk - - - - 150 - - qc charge injection - - - 820 - - - pc v pp = +40v, v nn = -160v, v sig = 0v - - - 600 - - - v pp = +100v, v nn = -100v, v sig = 0v - - - 350 - - - v pp = +160v, v nn = -40v, v sig = 0v supertex inc. www .supertex.com
5 doc.# dsfp-hv20320 c071613 hv20320 logic timing waveforms da ta in clock da ta out d n-1 d n d n+1 50% 50% 50% 50% 50% 50% 50% 50% 50% v out (typ) off on clr t wcl 90% 10% t off t dd t su t sd t on su t wle le t h truth table d0 d1 d2 d3 d4 d5 d6 d7 le clr sw0 sw1 sw2 sw3 sw4 sw5 sw6 sw7 l l l off h l l on l l l off h l l on l l l off h l l on l l l off h l l on l l l off h l l on l l l off h l l on l l l off h l l on l l l off h l l on x x x x x x x x h l hold previous state x x x x x x x x x h all switches off notes: 1. the eight switches operate independently. 2. serial data is clocked in on the l to h transition of the clk. 3. the switches go to a state retaining their present condition at the rising edge of le. when le is low the shift register data fow through the latch. 4. d out is high when data in the shift register 7 is high. 5. shift register clocking has no effect on the switch states if le is high. 6. the clr clear input overrides all other inputs. supertex inc. www .supertex.com
6 doc.# dsfp-hv20320 c071613 hv20320 test circuits switch off leakage v pp 5.0v v nn vpp vnn vdd gnd dc offset on/off t on /t off t est circuit v pp -10v r l 10kw v out i id v nn v sig v in = 10v p-p @5.0mhz nc 50w 50w v sig v out 1000pf q = 1000pf x v out charge injection v out output v oltage spike v out 1kw r l 50w +v spk -v spk r l v out 5.0v vpp vnn vdd gnd 5.0v vpp vnn vdd gnd 5.0v vpp vnn vdd gnd 5.0v vpp vnn vdd gnd 5.0v vpp vnn vdd gnd 5.0v vpp vnn vdd gnd 5.0v vpp vnn vdd gnd isolation diode current k cr = 20log v out v in crosstalk k o = 20log v out v in off isolation i sol v pp -10v v out v nn +10v r load 100k r l v in = 10v p-p @5.0mhz v pp v nn v pp v nn v pp v nn v pp v nn v pp v nn v pp v nn v pp v nn supertex inc. www .supertex.com
7 doc.# dsfp-hv20320 c071613 hv20320 typical performance curves clk frequency (khz) t do (ns) ambient temperature ( o c) r on () @5.0ma off-isolation (db ) -80.0 -75.0 -70.0 -65.0 -60.0 -55.0 -50.0 1.0 10.0 r on vs v pp /v nn v dd = 5.0v i pp /i nn average current (ma) output switching frequency (khz ) i dd current (ma) i dd vs clock frequency v dd = 5.0v, v pp /v nn = 100v, t a = 0 to 70 o c 3.0 2.0 1.0 0.0 10 1000 10000 100 signal voltage frequency (mhz ) v pp v nn t a = 0 o c t a = 25 o c t a = 70 o c t a = 125 o c t a = 70 o c -50- 25 02 55 07 5 100 125 150 0 10.0 20.0 30.0 40.0 i sw = 5.0ma 40v 60v 80v 100v 120v 140v 160v 0 10.0 20.0 30.0 40.0 50.0 -160v -140v -120v -100v -80v -60v -40v -50- 25 02 55 0 75 100 125 0 20 40 60 80 100 v dd = 5.0v 02 55 07 5 100 125 150 0 1 2 3 4 5 r on vs ambient temperature (t a ) v dd = 5.0v, v pp /v nn = 100v t a = 0 o c off-isolation vs signal voltage frequenc y v dd = 5.0v, v pp /v nn = 100v t a = 125 o c t a = 25 o c t a = 85 o c t a = 0 o c t do vs ambient temperature (t a ) v pp /v nn = 100v v dd = 13.5v ambient temperature ( o c) i pp /i nn vs output switching frequenc y v dd = 5.0v, v pp /v nn = 100v i sw = 200ma r on () supertex inc. www .supertex.com
8 doc.# dsfp-hv20320 c071613 hv20320 pin description pin # name pin # name 1 sw3 15 n/c 2 sw3 16 din 3 sw2 17 clk 4 sw2 18 le 5 sw1 19 cl 6 sw1 20 dout 7 sw0 21 sw7 8 sw0 22 sw7 9 vpp 23 sw6 10 vnn 24 sw6 11 n/c 25 sw5 12 gnd 26 sw5 13 vdd 27 sw4 14 n/c 28 sw4 supertex inc. www .supertex.com
9 hv20320 (the package drawing(s) in this data sheet may not refect the most current specifcations. for the latest package outline information go to http://www.supertex.com/packaging.html .) doc.# dsfp-hv20320 c071613 28-lead plcc package outline (pj) .453x.453in. body, .180in. height (max), .050in. pitch symbol a a1 a2 b b1 d d1 e e1 e r dimension (inches) min .165 .090 .062 .013 .026 .485 .450 .485 .450 .050 bsc .025 nom .172 .105 - - - .490 .453 .490 .453 .035 max .180 .120 .083 .021 .032 .495 .456 .495 .456 .045 jedec registration ms-018, variation ab, issue a, june, 1993. drawings not to scale . supertex doc. #: dspd-28plccpj, version b031111. .150max .048/.042 x 45 o .075max d d1 e1 e t op vi ew v iew b a a2 a1 seating plane note 1 (index area) .056/.042 x 45 o base plane .020min b vi ew b b1 horizontal side v iew v ertical side vi ew note 2 .020max (3 places) r e 4 26 28 1 notes: 1. a pin 1 identifer must be located in the index area indicated. the pin 1 identifer can be: a molded mark/identifer; an embedded metal marker; or a printed indicator. 2. actual shape of this feature may vary. supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such appl ications unless it receives an adequate ?product liability indemnification insurance agreement.? supertex inc. does not assume responsibility for use of devices described, and limits its liabilit y to the replacement of the devices determined defective due to workmanship. no responsibility is assumed for possible omissions and inaccuracies. circuitry and specifications are subject to change without notice. for the latest product specifications refer to the supertex inc. (website: http//www .supertex.com) ?2013 supertex inc. all rights reserved. unauthorized use or reproduction is prohibited. supertex inc. 1235 bordeaux drive, sunnyvale, ca 94089 t el: 408-222-8888 www .supertex.com
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